Stars
Experiments and prototypes associated with IREE or MLIR
TFLM examples using Renesas microcontrollers
Instruction Set Generator initially contributed by Futurewei
Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
Random instruction generator for RISC-V processor verification
Infrastructure to enable deployment of ML models to low-power resource-constrained embedded targets (including microcontrollers and digital signal processors).
Person Detection using HOG Feature and SVM Classifier
Implement a ChatGPT-like LLM in PyTorch from scratch, step by step
RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Compliance test).
TEMPORARY FORK of the riscv-compliance repository
平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）
C library for the emulation of reduced-precision floating point types
GNU toolchain for RISC-V, including GCC
SystemVerilog Functional Coverage for RISC-V ISA
Functional verification project for the CORE-V family of RISC-V cores.
Tools for embedded/bare-metal development using bazel
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
This is the main repository for all the examples for the book Practical UVM