Started a new repo for AXI to APB bridge

This repository presents a robust implementation of an AXI to APB bridge (AXI2APB) using Verilog HDL, complemented by a complete digital design flow incorporating RTL simulation, logic synthesis, s…

An AXI4 crossbar implementation in SystemVerilog

RISC-V CPU Core

RISC-V XV6/Linux SoC, marchID: 0x2b

Like VexRiscv, but, Harder, Better, Faster, Stronger

Repo that shows how to use the VexRiscv with OpenOCD and semihosting.

Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。

The RIFFA development repository

Digital FM Radio Receiver for FPGA

Build a SDR SW/MW/LW Receiver with a Raspberry Pi Pico

通用IO测试工程，用于捡垃圾测试IO。与BSDL需要对引脚输入不同，该工程只需要确定时钟输入，然后自动向每个IO发送指定字符串，因此只需要将串口接入任意IO查看输出即可

Build your hardware, easily!

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

A FPGA friendly 32 bit RISC-V CPU implementation

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Blind&Invisible Watermark ，图片盲水印，提取水印无须原图！

这里是 Yunzai-Bot 的扩展插件库

Enjoy the magic of Diffusion models!

An Implementation of NTQQ Protocol, with Pure C#, Derived from Konata.Core

支持国密SM2/SM3/SM4/SM9/SSL的密码工具箱

A shell script which convert gfwlist into dnsmasq rules. Python version: https://github.com/cokebar/gfwlist2dnsmasq_python

OSS implementation of the TCG TPM2 Software Stack (TSS2)

The source repository for the Trusted Platform Module (TPM2.0) tools

Linux kernel source tree

CasaOS - A simple, easy-to-use, elegant open-source Personal Cloud system.

Universal utility for programming FPGA

vits2 backbone with multilingual-bert

Community's fork of Loongson PMON bootloader