Skip to content
View Fvvrte's full-sized avatar
👋
👋

Block or report Fvvrte

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

synthesiseable ieee 754 floating point library in verilog

Verilog 705 157 Updated Mar 13, 2023

STM32 HAL-based library for SDHC/SDXC-cards

C 71 23 Updated Jun 17, 2020

EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.

90 31 Updated Mar 10, 2024

Rocket and Spacecraft Dynamics Modeling using DimTypes

C++ 12 2 Updated Nov 21, 2025

Yet another implementation of Dimension Types in C++, using a Z_p field for rational exponents encoding

C++ 13 3 Updated Oct 19, 2025

Attitude estimation using madgwick filter

MATLAB 17 12 Updated Nov 10, 2016

A server software for ArcheAge written in .Net Core

C# 384 237 Updated Dec 24, 2025

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog 950 326 Updated Nov 15, 2024
Python 8 2 Updated Apr 1, 2025

GNU toolchain for RISC-V, including GCC

C 4,287 1,332 Updated Dec 18, 2025

Official reference C / C++ library for the v2 protocol

C 289 496 Updated Dec 18, 2025

The decentralized package manager for C++ and friends 🏝️

F# 950 31 Updated Dec 8, 2022