在vscode上的数字设计开发插件

SystemC/TLM-2.0 Co-simulation framework

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

Minimal DVI / HDMI Framebuffer

Re-coded Xilinx primitives for Verilator use

Verilog code of Loongson's GS132 core