PicoRV32 - A Size-Optimized RISC-V CPU

Must-have verilog systemverilog modules

HDL libraries and projects

SERV - The SErial RISC-V CPU

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

uvm AXI BFM(bus functional model)

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

CoreScore

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

FPGA exercise for beginners

Graphics demos

Xilinx Unisim Library in Verilog

Implementation of hardware cores—including encryption, PRNGs, DSP modules, and accelerators—developed in pure Verilog for reference. Each design is validated against official specifications and sup…

AD7606 driver verilog

A Real Time Clock core for FPGA's

QuSoC demo projects and template

FIPS 202 compliant SHA-3 core in Verilog

Hardware Formal Verification

Project and presentation for SpaceX Application

A simple spidergon network-on-chip with wormhole switching feature

Hardware implementation of the hash function md5

miniTB provides a friendly environment for RTL designers to smoke test their code

Simple HDL simulators benchmark

A personal journey to master RTL (Register Transfer Level) design in 100 days, focusing on Verilog, VHDL, simulation, and synthesis. This repo documents my daily progress, learnings, projects, and …