a collection of open sourced VHDL for cryptography

Evaluation code for confidential virtual machines (AMD SEV-SNP / Intel TDX)

Pin based tool for simulation of rack-scale disaggregated memory systems

CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation

Example External Element for SST to enable testing and as user sample

SST Structural Simulation Toolkit Parallel Discrete Event Core and Services

[FCCM 2025] Code Samples for InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs

TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.

Tengine is a lite, high performance, modular inference engine for embedded device

Fault injection emulator in Zynq

Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)

基于 Flask 的后台管理系统，可快速构建功能业务，为 python 开发者提供一个后台管理系统的模板。

A single-function multi-cycle MIPS simulator which achieved very limited instructions.

This repository is used to release the Labs of Computer Architecture Course from USTC

Apple GPU microarchitecture

PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration

Repository containing the guide and code for booting RISC-V full system linux using gem5.

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as…

A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching

How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design

NeuraChip Accelerator Simulator

Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).

Synthetic Traffic Models Capturing a Full Range of Cache Coherent Behaviour

HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-logic architectures across 2D, 2.5D, 3D and 3.5D integration

A minimal GPU design in Verilog to learn how GPUs work from the ground up

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