A simple implementation to APB stub

ARM中通过APB总线连接的UART模块

在arm m3内核外挂一个gpio模块和uart模块，利用ahb_lite总线连接，该工程在黑金FPGA开发板AX1025上测试成功

Area Optimized RV32IC CPU core with a single AHB-Lite master Interface for Data and Instructions

AHB Bus lite v3.0

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equ…

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Synthesizable Single-Cycle RISC-V SoC featuring an APB v3.0 Bridge, UART Controller, and hardware flow control. Designed in Verilog.

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

my neovim configuration

📚 A Neovim config designed from scratch to be understandable

CPU Design Based on RISCV ISA

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

This is for uvm_tb_gen

运用逻辑与界面分离的思想，使用pyqt5+socket模块编写图形化TCP/UDP/WEB通信工具。

The code for our newly accepted paper in Pattern Recognition 2020: "U^2-Net: Going Deeper with Nested U-Structure for Salient Object Detection."

Collect some IC textbooks for learning.

嗨！thesis！哈尔滨工业大学毕业论文LaTeX模板

TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.

SpotX Mac and Linux adblocker for the Spotify desktop client, in Bash

Opensource DDR3 Controller

IC design and development should be faster，simpler and more reliable

OpenXuantie - OpenE902 Core