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@ggerganov
Georgi Gerganov ggerganov
I like big .vimrc and I cannot lie

@ggml-org Sofia, Bulgaria

@starpu-runtime
StarPU Runtime starpu-runtime
StarPU: A Unified Runtime System for Heterogeneous Multicore Architectures

France

@injinj
Chris Anderson injinj

Rai Technology San Francisco

@nikic
Nikita Popov nikic

Red Hat Berlin, Germany

@ianlancetaylor
Ian Lance Taylor ianlancetaylor
Programmer

Berkeley, California, USA

@banach-space
Andrzej Warzyński banach-space
Compiler engineer. Mathematician in previous life. @_banach_space

@Arm-Software Scotland

@WangXuan95
Dr.W.X WangXuan95
PhD graduated from USTC // FPGA // Verilog // Data Compression // LLM newbie // Hope to bring better open source projects. Welcome to report bugs.

Univ. of Sci. & Tech. of China (USTC) China

@ikwzm
KAWAZOME Ichiro ikwzm
Retired FPGA Engineer

Japan

@oldratlee
李鼎 oldratlee
Nobody is perfect, Mmm~ I'm nobody and a new dad! ☕️Java🍩@Kotlin🐍@python🐚Shell💎@vim🦫@golang 🦏JS 👓C# 🦀@rust-lang 🛠C++ 🔞@scala 🍥@clojure📞@erlang

PDD @taobao @aliyun @alibaba Shanghai ⇌ Hangzhou Zhejiang, China

@TheLartians
Lars Melchior TheLartians
Hey there! I'm a physicist, entrepreneur and full stack engineer based in Berlin.

Berlin

@rachitnigam
Rachit Nigam rachitnigam
Incoming EECS professor at MIT. Creator of @calyxir. Up to no good.

Massachusetts Institute of Technology

@xiaoweiChen
xiaowei xiaoweiChen
Coder

China, Zhejiang, Hangzhou

@mattvenn
Matt Venn mattvenn
Engineer and Science Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member.

@YosysHQ-GmbH @TinyTapeout Valencia, Spain

@bperez77
Brandon Perez bperez77

Seattle, Washington

@mithro
Tim 'mithro' Ansell mithro
Founder and Leader of @timvideos

@wafer-space Adelaide, Australia

@alexforencich
Alex Forencich alexforencich

UC San Diego La Jolla, CA

@basicmi
Shan Tang basicmi
I have been working in IC industry since 2000. From mid-2016, I started working on IC for Deep Learning.

Beijing

@Paebbels
Patrick Lehmann Paebbels
Vice-Chair of the IEEE P1076 Working Group (VHDL Analysis and Standardization Group- VASG). I'm a VHDL expert and FPGA-technology trainer at @PLC2.

@PLC2 Bötzingen, Germany

@HuaizhengZhang
Hunter Zhang HuaizhengZhang
😹PhD@NTUsg ❤️ Focus on MLSys and LLM Agent

ByteDance Seed Bay Area

@staeiou
Stuart Geiger staeiou
assistant professor at UC San Diego

UC San Diego San Diego, CA

@fengbintu
Fengbin Tu fengbintu
I'm an Assistant Professor at HKUST, with the PhD degree from Tsinghua University. My research interests include AI Chip and Computing-in-Memory.

HKUST Hong Kong, China

@tomzbj
Zhang Hao tomzbj

TIPC, CAS Beijing

@SI-RISCV
SI-RISCV
Deprecated account, please go to @riscv-mcu for latest hbird e203 riscv support, @Nuclei-Software for commercial Nuclei RISC-V Software support

@riscv-mcu

@doonny
Dong Wang doonny
Prof. at The Heterogeneous Computing Lab of Beijing Jiaotong University

Beijing Jiaotong University Beijing, China

@mtmd
mtmd

Bay Area, California