VHDL 2008/93/87 simulator

VUnit is a unit testing framework for VHDL/SystemVerilog

GPL v3 2D/3D graphics engine in verilog

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

MEGA65 FPGA core

The Zylin ZPU