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利用verilog硬件描述语言实现mips五级流水线CPU设计，并实现20条基本指令和其他高级指令，

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FPGA模型机课程设计.doc
FPGA模型机课程设计.doc
 
 
LICENSE
LICENSE
 
 
README.md
README.md
 
 
cpu.v
cpu.v
 
 

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mipsCPU

利用verilog硬件描述语言实现mips五级流水线CPU设计，并实现20条基本指令和其他高级指令，

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利用verilog硬件描述语言实现mips五级流水线CPU设计，并实现20条基本指令和其他高级指令，

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