A minimal GPU design in Verilog to learn how GPUs work from the ground up

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Common SystemVerilog components

BaseJump STL: A Standard Template Library for SystemVerilog

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters

Tensor computing core