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Focusing
PhD Student @ ICT, CAS
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Institute of Computing Technology, Chinese Academy of Sciences
- Beijing
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12:46
(UTC +08:00) - lelecheung.github.io
Highlights
- Pro
Stars
10
stars
written in Scala
Clear filter
Open-source high-performance RISC-V processor
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
OpenXiangShan / XSAI
Forked from OpenXiangShan/XiangShanA fork of Xiangshan for AI