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The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )
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Verilog parallel CRC generation module with custom polynomial and variable width
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ip_amba_ahb_ms_rtl_v Public
RTL design for the AMBA AHB protocol.
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GENUVM Public
Automated script to generate a generic UVM testbench with compatible makefile and internal scripts.
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rtl_template_gen Public
Script to generate a verilog IP template for quick build ( supports makefile, compilefileist and more )
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mips-pro-adam Public
It's a simple verilog based MIPS microarchitecture hardware design.
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ip_vga_ctlr_v Public
VGA controller RTL ( soft ip ) in Verilog
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Verilog serial CRC generation module with custom polynomial and variable width
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Custom polynomial ( variable width ) LFSR ( Galios/Fib ) generator
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prune_uvmg Public
GUI based UVM Test Environment generation tool
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std_module Public
All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.
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