Verilog to Routing -- Open Source CAD Flow for FPGA Research

Source code of Ferrocene, safety-critical Rust toolchain

A static analyzer for Java, C, C++, and Objective-C

A native, user-mode, multi-process, graphical debugger.

Yosys Open SYnthesis Suite

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

nextpnr portable FPGA place and route tool

A safe, extensible ORM and Query Builder for Rust

Ray is an AI compute engine. Ray consists of a core distributed runtime and a set of AI Libraries for accelerating ML workloads.

An Open-source FPGA IP Generator

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Modular hardware build system

SystemVerilog compiler and language services

Test suite designed to check compliance with the SystemVerilog standard.

The HW-CBMC and EBMC Model Checkers for Verilog

VHDL compiler and simulator

A C systems toolkit where ownership is part of the API: explicit copy/move/delete semantics and data-oriented utilities.

OpenSTA engine

how to optimize some algorithm in cuda.

Structural Netlist API (and more) for EDA post synthesis flow development

A Rust machine learning framework.

stb single-file public domain libraries for C/C++

Lovely console emulator package for Windows

This is the Rust course used by the Android team at Google. It provides you the material to quickly teach Rust.

ABC: System for Sequential Logic Synthesis and Formal Verification

Open Logic FPGA Standard Library

Open source FPGA silicon