Stefan T. SakaSerbia

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ASIC Digital Design Engineer. Let's share knowledge and skills.

Achievements

5 stars written in Verilog

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Verilog 832 204 Updated Apr 15, 2020

Implementation of CORDIC Algorithms Using Verilog

Verilog 24 2 Updated Apr 26, 2021

Implementation of Sobel Filter in Verilog

Verilog 24 14 Updated Mar 10, 2017

A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.

Verilog 16 2 Updated Apr 25, 2024

FPGA implementation of Real-time Ethernet communication using RMII Interface

Verilog 14 7 Updated Sep 18, 2014