A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Functional verification project for the CORE-V family of RISC-V cores.

A CPU tool for benchmarking the peak of floating points

LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作品）

2021年全国大学生计算机系统能力大赛—— 编译系统设计赛（华为毕昇杯）中，Calcifer队伍的作品

Optimizing compiler from a C subset to LLVM IR or ARM