Week 3 tasks for VSDBabySoC: Post-Synthesis Gate-Level Simulation (GLS) and Static Timing Analysis (STA) using Yosys, Icarus Verilog, GTKWave, and OpenSTA.

Week 2 educational and practical modules for VSDBabySoC — an open-source RISC-V based System-on-Chip using SkyWater Sky130. Covers SoC fundamentals, functional modelling, and pre-synthesis simulati…

Week 1 covers environment setup, open-source EDA tool installation, and Verilog RTL basics. Participants learn Linux commands, simulation flow, and simple testbenches, building a solid foundation f…

MicrowattSense: An open-source, low-power edge AI SoC built on the Microwatt POWER CPU. Integrates real-time sensor fusion, accelerators, and SKY130-ready RTL for reproducible, tapeout-ready design…

Documentation and implementation of the RISC-V SoC Tapeout Program by VSD, including design files, RTL, scripts, results, and supporting media related to Digital VLSI and SoC design flow.

Professional mobile app for crowd monitoring and emergency management

Professional mobile app for crowd monitoring and emergency management

A 4-bit ALU in VHDL for Spartan-6 FPGA, tested with onboard switches and LEDs, verified in Vivado and hardware.

🌱💧 An IoT-based Smart Plant Monitoring and Watering System using ESP32, Soil Moisture Sensor, Relay, Motor, and Blynk App for real-time monitoring and control.

Design and Simulation of a 4-bit Carry Select Adder using MTCMOS-based 10T Full Adders and Ripple Carry Architecture in Cadence Virtuoso

Low-power full adder using 10 transistors and MTCMOS in Cadence Virtuoso

Design and Simulation of a 4-Bit Ripple Carry Adder using MTCMOS-Based 10T Full Adders in Cadence Virtuoso for Low-Power VLSI Applications

Low-power full adder using 10 transistors and MTCMOS in Cadence Virtuoso

Automated Plant Watering System