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A machine learning accelerator core designed for energy-efficient AI at the edge.

Emacs Lisp 1,953 214 Updated Dec 19, 2025

The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso

52 9 Updated Mar 21, 2024

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

1,272 128 Updated Nov 6, 2025

A reading list for SRAM-based Compute-In-Memory (CIM) research.

108 7 Updated Oct 29, 2025

linux initramfs, testing, openocd, and other random utils for openrisc

Shell 6 Updated Jun 3, 2025

IC implementation of Systolic Array for TPU

Verilog 317 34 Updated Oct 21, 2024

all material for the VSD-HDP program

Verilog 3 Updated Dec 17, 2023

VSD FPGA Based Maze Solving Robot Design and Development.

Verilog 3 1 Updated Aug 4, 2025

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Verilog 118 9 Updated Dec 17, 2023

Chisel: A Modern Hardware Design Language

Scala 4,512 643 Updated Dec 21, 2025

Learn about the Neumorphic engineering process of creating large-scale integration (VLSI) systems containing electronic analog circuits to mimic neuro-biological architectures.

Python 545 77 Updated Jan 4, 2024

8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at r…

12 4 Updated Jul 21, 2022

Build your hardware, easily!

C 3,649 673 Updated Dec 20, 2025
Verilog 4 Updated May 20, 2025

2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)

Verilog 30 25 Updated Apr 13, 2024

List of awesome semiconductor startups

Python 687 117 Updated Jul 29, 2025
Verilog 2 2 Updated May 13, 2025
C 13 6 Updated Apr 13, 2025

SERV - The SErial RISC-V CPU

Verilog 1,710 240 Updated Dec 16, 2025

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,840 887 Updated Jun 27, 2024

Code for VSDSquadron_FM

C 2 11 Updated Apr 5, 2025

Your neuro-rehabilitation platform. Recovering from a stroke, brain injury, or other neurological conditions, we offer personalized plans, virtual therapy, and support tools

Python 8 2 Updated Mar 6, 2025

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

SystemVerilog 184 39 Updated Nov 18, 2024

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally …

Verilog 23 4 Updated Jan 23, 2024

Learning FPGA, yosys, nextpnr, and RISC-V

C++ 3,338 316 Updated Nov 18, 2025

Verilog interface for HC-SR04 Ultrasonic Ranging Module

Verilog 8 8 Updated Aug 3, 2023

A guide for installing the Keil ARM MDK on macOS and Linux

154 14 Updated Apr 5, 2023

Code for VSDSquadron_FM

C 5 4 Updated Jan 24, 2025

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical i…

HTML 284 60 Updated May 30, 2025
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