PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog PCI express components

RISC-V XV6/Linux SoC, marchID: 0x2b

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

VRoom! RISC-V CPU

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

Mega Drive/Genesis core written in Verilog

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Verilog UART

Amiga Minimig ported to the Tang Nano 20k FPGA

Turbo9 - Pipelined 6809 Microprocessor IP

This repository contains small example designs that can be used with the open source icestorm flow.

IceChips is a library of all common discrete logic devices in Verilog

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)

Pong game in a FPGA.

IP operations in verilog (simulation and implementation on ice40)

A display latency measurement tool

Integrated System for Enhancing VIC Output

Reverse-engineering of SEGA chips

TV80 Z80-compatible microprocessor

AD7606 driver verilog

FLIX-V: FPGA, Linux and RISC-V