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  • University of Southampton
  • Southampton, United Kingdom
  • LinkedIn in/talha-israr

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TalhaIsrar/README.md

👋 Hi, I'm Talha Israr

I'm an Hardware Design Engineer passionate about processor design, RTL verification, and embedded systems. I enjoy bridging the gap between digital design theory and real-world FPGA/SoC implementations, turning ideas into reliable, high-performance hardware.

🎓 Currently pursuing an Erasmus Mundus Joint Master’s in Embedded Computing Systems (EMECS) while working on hardware design projects in my free time.

🛠️ Technical Skills

🧩 Hardware Description Languages: SystemVerilog · Verilog · VHDL · Chisel

⚙️ Tools & Simulation: Vivado Design Suite · Vitis HLS · Quartus . ModelSim · OneSpin

🔗 Embedded Systems & AI: FPGA · Raspberry Pi · Jetson Nano/TX2/AGX · Edge AI Deployment

🔌 Circuit Simulation & Design: LTspice · Multisim · Proteus · MATLAB

💻 Programming: C · C++ · Python · R · RISC-V Assembly

📊 Data & ML: PyTorch · TensorFlow · SQL · Tableau · Power BI

🧩 Key Interests:

🚀 Pipelined Processor design, branch prediction, hazards & extensions
🧠 AMBA Protocols & peripheral interfacing
🔐 Hardware acccelerator development

“Design for performance. Verify for reliability.”
🧩 Always open to collaborations in digital design, verification, and embedded AI.

Pinned Loading

  1. RISCV-RV32IM-AXI4-Lite-SoC RISCV-RV32IM-AXI4-Lite-SoC Public

    SystemVerilog 14 4

  2. RISCV_Benchmarking_framework RISCV_Benchmarking_framework Public

    C 2

  3. AMBA_Protocols AMBA_Protocols Public

    SystemVerilog 4

  4. Memory_Protection_Codes Memory_Protection_Codes Public

    Verilog 1

  5. RISCV-RV32IM-5-Stage-Pipelined-Processor RISCV-RV32IM-5-Stage-Pipelined-Processor Public

    Verilog 2

  6. RISCV_Branch_Target_Buffer RISCV_Branch_Target_Buffer Public

    Scala