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Starred repositories

4 results for source starred repositories written in Verilog
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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 2,253 728 Updated Nov 6, 2025

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Verilog 510 391 Updated Nov 5, 2025

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

Verilog 49 16 Updated Jan 4, 2022

Jade CGRA using NEM relay interconnect fabric. Related repositories: NEM-Relay-CGRA-Flow, NEM-Relay-CAD

Verilog 9 4 Updated Aug 15, 2021