VHDL 2008/93/87 simulator

All in one vscode plugin for HDL development

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

A huge VHDL library for FPGA and digital ASIC development

VHDL synthesis (based on ghdl)

VHDL Guide

FPGA implementation of the Apollo Guidance Computer