Pinned Loading

1. Note Note Public

   Walker_V's Notebook

   HTML 7

2. FPGA-clock-attached-chess FPGA-clock-attached-chess Public

   浙江大学「数字逻辑设计」课程大作业：基于 FPGA 的附棋钟国际象棋

   Verilog 7 1

3. DL-DRPE-Recognition DL-DRPE-Recognition Public

   A deep learning framework for matching original grayscale images and their encrypted versions using Double Random Phase Encoding (DRPE) and Siamese networks (ResNet, ConvNeXt, ViT-CLIP).

   Python 1