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axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedNov 13, 2025 -
litepcie Public
Forked from enjoy-digital/litepcieSmall footprint and configurable PCIe core
Python Other UpdatedNov 5, 2025 -
verilog-axi Public
Forked from alexforencich/verilog-axiVerilog AXI components for FPGA implementation
Verilog MIT License UpdatedJul 21, 2025 -
ADI_hdl Public
Forked from analogdevicesinc/hdlHDL libraries and projects
Verilog Other UpdatedJul 8, 2025 -
verilog-axis Public
Forked from alexforencich/verilog-axisVerilog AXI stream components for FPGA implementation
Python MIT License UpdatedFeb 27, 2025 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
SystemVerilog Apache License 2.0 UpdatedNov 3, 2024 -
riscv-dv Public
Forked from chipsalliance/riscv-dvRandom instruction generator for RISC-V processor verification
Python Apache License 2.0 UpdatedAug 29, 2024 -
riffa Public
Forked from KastnerRG/riffaThe RIFFA development repository
Verilog Other UpdatedJun 11, 2024 -
verilog-pcie Public
Forked from alexforencich/verilog-pcieVerilog PCI express components
Verilog MIT License UpdatedApr 26, 2024 -
verilog-ethernet Public
Forked from alexforencich/verilog-ethernetVerilog Ethernet components for FPGA implementation
Verilog MIT License UpdatedMar 8, 2024 -
verilog-i2c Public
Forked from alexforencich/verilog-i2cVerilog I2C interface for FPGA implementation
Verilog MIT License UpdatedDec 13, 2023 -
openc910 Public
Forked from XUANTIE-RV/openc910OpenXuantie - OpenC910 Core
Verilog Apache License 2.0 UpdatedDec 5, 2023 -
gen_amba_2021 Public
Forked from adki/gen_amba_2021AMBA bus generator including AXI4, AXI3, AHB, and APB
C Other UpdatedJul 16, 2023 -
AHB-to-APB-Bridge-Verification Public
Forked from Siddhi-95/AHB-to-APB-Bridge-VerificationMaven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
SystemVerilog UpdatedJul 2, 2023 -
e203_hbirdv2 Public
Forked from riscv-mcu/e203_hbirdv2The Ultra-Low Power RISC-V Core
Verilog Apache License 2.0 UpdatedMar 27, 2023 -
verilog-uart Public
Forked from alexforencich/verilog-uartVerilog UART
Verilog MIT License UpdatedMar 21, 2023 -
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AxiCores Public
Forked from Cognoscan/AxiCoresAXI4-Compatible Verilog Cores, along with some helper modules.
SystemVerilog Apache License 2.0 UpdatedMar 14, 2020 -
AMBA_APB_SRAM Public
Forked from courageheart/AMBA_APB_SRAMAMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
SystemVerilog MIT License UpdatedJul 23, 2018 -
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Embedded-And-Network Public
Forked from FutureMine/Embedded-And-Network嵌入式与网络研究组
UpdatedOct 28, 2017
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