Pan Jian
jiyiyan
I am a student majoring in Electronic Science and Technology at the School of Information Science and Electronic Engineering, Zhejiang University.
Arju Patil
arju-patil
ECE Graduate | Aspiring VLSI Design Engineer | Verilog · VHDL · RTL Design | Exploring chip design one module at a time
Chuann
ChuanN-sudo
Firmware & BSP engineer | RT-Thread / U-Boot | RISC-V & ARM
University of Chinese Academy of Sciences Beijing, China
雷航
crazylei12
An FPGA engineer working at a new-energy-related company; currently planning to learn and experiment with using AI to create content of personal interest.
Jiayt2004
Jsupermaster
Undergraduate from JLU. Incoming Ph.D. student at the ICT.
My research interests focus on AI Chip Design, FPGA Development, Computer Architecture.
Guo Xiangming
guoxmm
student of Jilin University
@jilin University
Jilin University Changchun,Jilin,China
Johnny Yao
yl120064227
I am JohnnyYao, a student in ZheJiang University of Technology. I am eager to learn on GitHub and contribute my part to this community
ZheJiang University of Technology No. 288, Liuhe Road, Xihu District, Hangzhou, Zhejiang Province, China
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