A Simple AMU using HBL2 as package.

Initialization:

git clone git@github.com:LeleCheung/HBL2-AMU-Demo.git  
cd HBL2-AMU-Demo
git submodule update --init --recursive

Chisel Test (test_run_dir/):

make test-top

Generate Verilog (build/):

make gen-top

Clean:

make clean

SIMPLE TEST:

• Init the register
• Store the data back to HBL2
• Load the data from HBL2
• Check the register value