Étudiant en Master 2 en électronique embarquée à l'Université de Lorraine || Ingénieur en mécatronique ||
-
Université de Lorraine
- Nancy - France
- in/yakkary
Popular repositories Loading
-
Single-Cycle-RV32I-RISC-V-Processor-UVM-Verification-Environment-Passive-Agents-
Single-Cycle-RV32I-RISC-V-Processor-UVM-Verification-Environment-Passive-Agents- PublicSingle‑cycle RV32I CPU in Verilog with a full UVM verification environment: passive instruction/data memory agents, dedicated ALU/control/PC/regfile/imm monitors, centralized scoreboard with golden…
SystemVerilog 1
-
project
project PublicTraduction du langage des signes oar ATMEGA32 microprocessor et Proteus Professional pour la simulation
C
-
cao_minimouse_2023
cao_minimouse_2023 PublicForked from Flo-beeionic/cao_minimouse_2023
Minimouse project for CAO Course
-
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.