A simple VHDL project implementing a 4-bit asynchronous binary counter with an accompanying testbench for simulation.
- BinaryCounter_4Bit_Asynchronous.vhd: Implements a 4-bit binary counter that counts on each rising clock edge and asynchronously resets when
CLRis high. - BinaryCounter_4Bit_Asynchronous_tb.vhd: Testbench simulating the counter’s behavior, including clock generation and periodic asynchronous resets.
| Signal | Direction | Type | Description |
|---|---|---|---|
| clock | in | STD_LOGIC |
Clock signal |
| CLR | in | STD_LOGIC |
Asynchronous reset |
| period | in | integer |
Simulation duration (TB) |
| Q | out | STD_LOGIC_VECTOR(3 downto 0) |
4-bit counter output |
- Counting Logic: Increments on each rising clock edge.
- Asynchronous Reset: Resets to 0 when
CLRis high.
- Clock Generation: Simulates a clock with a 20 ns period.
- Reset & Counting: Asserts
CLRfor reset and observes theQoutput over several cycles.
- Compile & Simulate: Import both
.vhdfiles into your VHDL simulator. - Run and Observe: Check the
Qoutput to see the counter in action.
- VHDL Compiler: Compatible with VHDL-93+
- Vivado (or any VHDL simulation tool)
Enjoy :)