Search results

Self-assigning case corrupts ternary selector synthesis

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5957 In YosysHQ/yosys;

· qinkejiu opened on Jun 12, 2026

Yosys crash when module output signal name same as module name

bug

fix-pendingPR with a fix is pendingPR with a fix is pending

Status: Open.

#5954 In YosysHQ/yosys;

· emeb opened on Jun 11, 2026

Wildcard package imports (import pkg::*) fail to resolve typedefs

enhancement

SystemVerilogIssues and questions related to SystemVerilogIssues and questions related to SystemVerilog

Status: Open.

#5947 In YosysHQ/yosys;

· warricklo opened on Jun 9, 2026

opt_clean misidentifies live latch-feeding mux logic as dead, causes simulation mismatch

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5946 In YosysHQ/yosys;

· zhihaoxu1325 opened on Jun 9, 2026

wreduce incorrectly narrows cells whose high bits are observable through concatenation bit-select

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5945 In YosysHQ/yosys;

· zhihaoxu1325 opened on Jun 9, 2026

fsm pass corrupts transparent latch enable logic, swapping hold and update conditions

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5942 In YosysHQ/yosys;

· zhihaoxu1325 opened on Jun 8, 2026

opt_clean after proc changes simulation result for explicitly-driven output bit

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5941 In YosysHQ/yosys;

· zhihaoxu1325 opened on Jun 8, 2026

techmap: incorrect lowering of unsigned $mod via $__div_mod_u produces wrong simulation result

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5940 In YosysHQ/yosys;

· zhihaoxu1325 opened on Jun 8, 2026

Follow up to #5906 Nexus DSP techmap is missing MULT* register absorption

feature-request

Status: Open.

#5917 In YosysHQ/yosys;

· agentdavo opened on May 29, 2026

Empty always @* constant assignment changes RTL/netlist behavior through inversion

needs-external-contribution

SystemVerilogIssues and questions related to SystemVerilogIssues and questions related to SystemVerilog

Status: Open.

#5916 In YosysHQ/yosys;

· qinkejiu opened on May 29, 2026

proc is not infering $_DLATCH_[NP][NP][01]_ type lathes properly

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5910 In YosysHQ/yosys;

· jeras opened on May 27, 2026

Incorrect Netlist Transformation in muxpack Pass

bug

Status: Open.

#5864 In YosysHQ/yosys;

· moffel opened on May 9, 2026