Tried building examples on Fedora 43, which has Verilator 5.046.
I get a lot of warnings with 'SYNCASYNCNET' which prevented it from building, and after disabling those, I got more 'logical-op' errors from g++.
Example:
%Warning-SYNCASYNCNET: ../../rtl/axivdisplay.v:285:10: Signal flopped as both synchronous and async: 'axidemo.video.videodma.arskd_valid'
../../rtl/axivideo.v:682:7: ... Location of async usage
682 | if (!S_AXI_ARESETN)
| ^~~~~~~~~~~~~
axidemo.v:251:1: ... note: In file included from 'axidemo.v'
demofull.v:350:7: ... Location of sync usage
350 | if (!S_AXI_ARESETN)
| ^~~~~~~~~~~~~
... For warning description see https://verilator.org/warn/SYNCASYNCNET?v=5.046
... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this messageand then, for the logical-op error:
In file included from Vaxidemo__ALL.cpp:4:
Vaxidemo___024root__0.cpp: In function ‘void Vaxidemo___024root___nba_sequent__TOP__0(Vaxidemo___024root*)’:
Vaxidemo___024root__0.cpp:715:50: error: logical ‘and’ of equal expressions [-Werror=logical-op]
715 | = ((1U & (~ (IData)(vlSelfRef.i_reset))) &&
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
716 | (1U & (~ (IData)(vlSelfRef.i_reset))));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1plus: all warnings being treated as errors
make[2]: *** [/usr/share/verilator/include/verilated.mk:280: Vaxidemo__ALL.o] Error 1
make[1]: *** [Makefile:75: obj_dir/Vaxidemo__ALL.a] Error 2
make: *** [Makefile:50: demo] Error 2This is the fix I did to get it compiling, but this is sort of just the lazy band-aid on the issue:
diff --git a/bench/rtl/Makefile b/bench/rtl/Makefile
index a9d99ab..8de0d70 100644
--- a/bench/rtl/Makefile
+++ b/bench/rtl/Makefile
@@ -61,7 +61,8 @@ VERILATOR := verilator
else
VERILATOR := $(VERILATOR_ROOT)/bin/verilator
endif
-VFLAGS := -Wall --MMD -O3 --trace -y ../../rtl -cc
+VFLAGS := -Wall -Wno-SYNCASYNCNET --MMD -O3 --trace -y ../../rtl -cc -CFLAGS "-Wno-error=logical-op"
+
## Generic rules
## {{{
diff --git a/rtl/Makefile b/rtl/Makefile
index 02d054c..12a7c47 100644
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -51,7 +51,7 @@ VERILATOR := verilator
else
VERILATOR := $(VERILATOR_ROOT)/bin/verilator
endif
-VFLAGS := -Wall --MMD --trace -cc
+VFLAGS := -Wall -Wno-SYNCASYNCNET --MMD --trace -cc
$(VDIRFB)/Vwbvgaframe__ALL.a: $(VDIRFB)/Vwbvgaframe.h
$(VDIRFB)/Vwbvgaframe__ALL.a: $(VDIRFB)/Vwbvgaframe.cpp
Tried building examples on Fedora 43, which has Verilator 5.046.
I get a lot of warnings with 'SYNCASYNCNET' which prevented it from building, and after disabling those, I got more 'logical-op' errors from g++.
Example:
and then, for the logical-op error:
This is the fix I did to get it compiling, but this is sort of just the lazy band-aid on the issue: