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bit by bit
step by step
Msc. in Computer Science @ UFMG - Nanocomp Lab.
- Belo Horizonte, Minas Gerais, Brazil
- https://www.linkedin.com/in/marco-tulio-sm/
- https://nanocomp.dcc.ufmg.br
Highlights
- Pro
Stars
2
stars
written in SystemVerilog
Clear filter
Verilator open-source SystemVerilog simulator and lint system
SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software