i hated checking and signing into brightspace so i built an mcp server connection to Poke[@interactionco]

32-bit Superscalar RISC-V CPU

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

adammaj.com | Built with Next & Chakra

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Python-like test style while potentially improving simulation p…

ECE 350: Real-Time Operating Systems

Verilog HDL implementation of SDRAM controller and SDRAM model

RTL code and testbenches for a toy ML accelerator comparing dataflows

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Resources to Prepare for Quant Developers/ Quantitative Researcher/ Quantitative Trader/ Quant Analyst/ Software Engineers in Quant Trading Firms, HFTs and Hedge Funds

Book: Quantum Computing Architecture and Hardware for Engineers - Step by Step

Everything you need to extend Raycast.

MLX: An array framework for Apple silicon

IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.

SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)

Common SystemVerilog components

SystemVerilog Assertion (SVA) based formal verification suite for subset of RISCV RV32I

This repository is compilation of basics of System Verilog Assertions in context of formal verification

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

The open-source CapCut alternative

A very simple and easy to understand RISC-V core.

OpenSTA engine

Basic RISC-V Test SoC

The official repository for the gem5 computer-system architecture simulator.

htop - an interactive process viewer