Skip to content
View markblz's full-sized avatar

Block or report markblz

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

11 stars written in Verilog
Clear filter

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Verilog 620 103 Updated Jan 3, 2020

Verilog Generator of Neural Net Digit Detector for FPGA

Verilog 314 91 Updated Sep 7, 2022
Verilog 296 91 Updated Mar 3, 2024

Implementation of CNN using Verilog

Verilog 233 85 Updated Oct 13, 2017

Fully opensource spiking neural network accelerator

Verilog 162 19 Updated Feb 13, 2023

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management modul…

Verilog 158 36 Updated Apr 25, 2024

DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.

Verilog 96 39 Updated Nov 7, 2020

Yet Another Tetris on FPGA Implementation

Verilog 40 17 Updated May 27, 2021

A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.

Verilog 18 6 Updated Oct 11, 2019

FPGA Verilog HDL design project (DE1-SoC)

Verilog 13 1 Updated Jan 19, 2018

Implementation of Hopfield network using Verilog

Verilog 4 Updated Nov 18, 2019