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Buzz transcribes and translates audio offline on your personal computer. Powered by OpenAI's Whisper.

Python 19,314 1,421 Updated May 16, 2026

Home Assistant integration for Dreame robot vacuums with map support

Python 1,952 234 Updated Apr 26, 2026

User space mappable dma buffer device driver for Linux.

C 687 186 Updated Mar 12, 2026

Verilog AXI stream components for FPGA implementation

Python 892 271 Updated Feb 27, 2025

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

VHDL 152 25 Updated May 16, 2026

Xilinx Embedded Software (embeddedsw) Development

HTML 1,188 1,141 Updated May 19, 2026

High Speed Data Acquisition over HDMI - FPGA implementation

Verilog 57 9 Updated Mar 8, 2026

A collection of Master XDC files for Digilent FPGA and Zynq boards.

Tcl 671 586 Updated Nov 12, 2024

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

Verilog 115 25 Updated Feb 22, 2024

ASIC implementation flow infrastructure, successor to OpenLane

Python 408 72 Updated May 13, 2026

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Python 1,793 431 Updated Mar 25, 2026

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 2,681 897 Updated May 20, 2026

Build reliable Gen AI solutions without overhead 🍕

Python 2,205 135 Updated May 19, 2026

A MNIST-like fashion product database. Benchmark 👇

Python 12,733 3,070 Updated Jun 13, 2022

Official implementation of DeepLabCut: Markerless pose estimation of user-defined features with deep learning for all animals incl. humans

Python 5,639 1,782 Updated May 20, 2026

Verilator open-source SystemVerilog simulator and lint system

SystemVerilog 3,622 815 Updated May 20, 2026

Icarus Verilog

C++ 3,453 604 Updated May 17, 2026

G-code generator for 3D printers (RepRap, Makerbot, Ultimaker etc.)

C++ 9,052 2,253 Updated May 19, 2026

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VHDL 713 68 Updated Dec 14, 2025

Hdl is a tool for easing the work with hardware description languages.

Go 12 Updated Dec 12, 2022

Windows software for sharing locally connected USB devices to other machines, including Hyper-V guests and WSL 2.

C# 5,723 352 Updated May 14, 2026

A VHDL specification of a CORDIC interface used to calculate the atan2 value from a pair of coordinates.

VHDL 5 Updated Jul 28, 2017

🖥 Delightful Hyper plugins, themes, and resources

10,954 371 Updated Sep 20, 2022

Neo is a package for representing electrophysiology data in Python, together with support for reading a wide range of neurophysiology file formats

Python 361 272 Updated May 18, 2026

A VSCode extension that allows you to use ChatGPT

TypeScript 4,943 362 Updated Sep 29, 2023

Simple led blinker companion project developed for a blog post

VHDL 3 Updated May 25, 2023

OSVVM Documentation

37 9 Updated Mar 1, 2026

Starter files, final projects, and FAQ for my HTML + CSS course

HTML 3,050 2,343 Updated Aug 10, 2024

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

VHDL 258 74 Updated May 15, 2026
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