The NYU ProcDesign Core will be a RISCV-32I compatible core with a 5 stage pipeline.

The repo contains the modules and test for components that make up the core design.

The core modules include:

• Arithmatic Logic Unit (ALU)
• General Registers
• Program Counter

The branch logic modules include:

• Branch Evaluator
• Branch Predictor
• Branch Address Calculator
• Branch Manager

The pipeline will have 5 stages:

• Instruction Fetch (IF)
• Instuction Decode (ID)
• Execution (EX)
• Memory Access (MEM)
• Write Back (WB)

The pipeline will require 4 latch modules:

• IF/ID Latch
• ID/EX Latch
• EX/MEM Latch
• MEM/WB Latch

Control Modules:

• Processor State Module
• Pipeline Reset Module

Cache Modules:

• Instruction Cache Manager
• L1 Instruction Cache
• Data Cache Manager
• L1 Data Cache
• L2 Data Cache
• L3 Data Cache

Development and Testing Guidelines

Offical RISCV Unprivileged Instruction Set Documentation