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@infiniband
infiniband
@vikasb160
vikasb160
@Opadc
Opadc Opadc
code is hard, i prefer for talk

BeiJing

@violinlym
violinlym
@sura-sivareddy
SURA SIVAREDDY sura-sivareddy
Masters in Electrical Engineering @ IIT Kanpur
@KhoiNPh
Pham Ngoc Khoi Nguyen KhoiNPh
@fangwenji
Wenji Fang fangwenji
Ph.D. Student @ HKUST

The Hong Kong University of Science and Technology Hong Kong

@luei1987kg
luei&july luei1987kg

chengdu

@danielchacon9925
Daniel Chacón Mora danielchacon9925
Passionate electrical engineer from the Universidad de Costa Rica.

San José, Costa Rica

@buffteethr
buffteethr
@Raunak-727
Raunak Malapure Raunak-727
student

student Nagpur ,

@pavan-kalyan-durga
D pavan kalyan pavan-kalyan-durga
@AshishThakur2408
Ashish Thakur AshishThakur2408
An enthusiastic VLSI RTL Design engineer, Post graduated from NIT Warangal in 2018.
@mshahbazhussain
Shahbaz Hussain mshahbazhussain
Interested in • Low-power Energy-Efficient circuits • Spintronics • Hardware security • FPGA H/w implementation • Approximate computing

AMU Aligarh

@kish97
Kishore Pula kish97
@Pavankmp
Pavan Km Pavankmp
Verilog | system Verilog | UVM | FPGA

Banglore

@yedk
yedk
@joeyahines
Joey Hines joeyahines
Space is cool.
@pardhu29
pardhu29
@jhmorris3486
jhmorris3486