Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

GPGPU supporting RISCV-V, developed with verilog HDL

OpenXuantie - OpenC910 Core

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Verilog AXI components for FPGA implementation