AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Common SystemVerilog components

The root repo for lowRISC project and FPGA demos.

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

VeeR EL2 Core

RISC-V Debug Support for our PULP RISC-V Cores

Demo SoC for SiliconCompiler.

The SoC used for the beta phase of Hack@DAC 2018.

The SoC used for the beta phase of Hack@DAC 2018.