A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one

An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器，用于通用数据压缩。

LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.

Let's write an OS which can run on RISC-V in Rust from scratch!

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

GNU toolchain for RISC-V, including GCC

Submission template for Tiny Tapeout 9 - Verilog HDL Projects

Verilog Ethernet components for FPGA implementation

RISC-V Nox core

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Universal Memory Interface (UMI)

A Linux-capable RISC-V multicore for and by the world

VeeR EL2 Core

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Basic USB 1.1 Host Controller for small FPGAs

Bitmap Processing Library & AXI-Stream Video Image VIP

RISC-V XV6/Linux SoC, marchID: 0x2b

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

Functional verification project for the CORE-V family of RISC-V cores.

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

FPGA based microcomputer sandbox for software and RTL experimentation

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

RISC-V RV32IMAFC Core for MCU

BaseJump Open-Source Hardware Accelerator Packages and Sockets

Summer School Week 1 & 2 repo

Modular hardware build system