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This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization. MCP server for a collection of open-source EDA …
A library of common data structures and algorithms written in C.
A curated list of awesome MangoPi MQ-Pro images, tools and resources
This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator developm…
Hosted Solution (Linux/MCU) with ESP32 (Wi-Fi + BT + BLE)
Hello AI World guide to deploying deep-learning inference networks and deep vision primitives with TensorRT and NVIDIA Jetson.
ChatGLM3 series: Open Bilingual Chat LLMs | 开源双语对话语言模型
Hardware Security Module (HSM) for Raspberry Pico and ESP32
An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
Open source FPGA-based NIC and platform for in-network compute
FPGA verilog and firmware for TKey, the flexible and open USB security key 🔑
Apache NuttX RTOS for Pine64 Ox64 64-bit RISC-V SBC (BouffaloLab BL808)
Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k Mega 138K Pro Console60k/138k FPGA
Convert any LCSC components (including EasyEDA) to KiCad library
Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
Verilog I2C interface for FPGA implementation
🚀🚀🚀 This repository lists some awesome public CUDA, cuda-python, cuBLAS, cuDNN, CUTLASS, TensorRT, TensorRT-LLM, Triton, TVM, MLIR, PTX and High Performance Computing (HPC) projects.
Small footprint and configurable SATA core
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.