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1. learngit learngit Public

2. FPGA-UART FPGA-UART Public

   Forked from WangXuan95/FPGA-UART

   This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

   Verilog

3. ASIC-Design-Roadmap ASIC-Design-Roadmap Public

   Forked from abdelazeem201/ASIC-Design-Roadmap

   The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

   Verilog