A Hardware Description Language based on the Rust Programming Language

My curated list of projects using bevy in production, preferably with a company or a business model in mind.

A refreshingly simple data-driven game engine built in Rust

A typst package for creating diagrams of network protocols, memory layouts, register definitions or similar structures.

Fast and simple benchmarking for Rust projects

Better configuration for less

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

This unofficial extension integrates Draw.io (also known as diagrams.net) into VS Code.

🍰 bit field diagram renderer

Small footprint and configurable embedded FPGA logic analyzer

Pure C ONNX runtime with zero dependancies for embedded devices

Useful set of library functions for VHDL

FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)

😎 Awesome lists about all kinds of interesting topics

Hardware Description Languages

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Library of VHDL components that are useful in larger designs.

🚂 A small JS+SVG library for drawing railroad syntax diagrams, like on JSON.org. Now with a Python port!

Flexible VHDL library

Open source patient monitor based the esp32

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!