Verilog Ethernet components for FPGA implementation

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

IC design and development should be faster，simpler and more reliable

Verilog AXI components for FPGA implementation

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

NetFPGA 1G infrastructure and gateware

Open source FPGA-based NIC and platform for in-network compute

5-stage pipelined 32-bit MIPS microprocessor in Verilog

TCP Offload Engine

Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC

Convolution Neural Network of vgg19 model in verilog

Gigabit MAC + UDP/TCP/IP offload Engine

Completed Verilog Pre-labs for the EECS2021 course at York University, Toronto, Canada

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.