VHDL 2008/93/87 simulator

Develop an end-to-end hypothetical reference model, network architectures, precision time tools, performance objectives and the methods to distribute, operate, monitor time synchronization within d…

VUnit is a unit testing framework for VHDL/SystemVerilog

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

A huge VHDL library for FPGA and digital ASIC development

Donjon hardware tool for circuits security evaluation

A simple I2C minion in VHDL

Everything to do with the XuLA FPGA board: schematics, layout, firmware, example FPGA designs, documentation, etc.

Transform the Red Pitaya in an acquisition card

Single Port RAM, Dual Port RAM, FIFO

I2C Slave Interface (Vhdl)

VHDL functional blocks with their simulations and test sequences

A very simple UART implementation in MyHDL

Graphical environment for Digital Signal Processing