I'm also interested in this PR for FuseSoC. It seems like changes to verilog source files aren't triggering a build. I have to pass --clean to fusesoc run ... every time. The source file in this case is coming from a generator (not cached).

AFAIR I had to make the project file an order-only dep because it kept getting updated by Vivado which meant that everything that depended on the XPR got unconditionally rebuilt even if nothing changed. Looking at it now, however I see that the current logic doesn't really make sense. Maybe we can change the project generation script to write out a marker file and use that instead of the xpr to track when we need to rebuild?

That makes sense.

When I tested this before, I beleive that the only thing that depended on the XPR file was the synthesis and implementation runs, but those runs check wheather or not they are complete before running. So, in practice, if nothing changed, nothing would be run.

On the other hand, in case something else depends on the XPR file, that recipe would be run again.

Your solution of adding a marker file seems good.