Repositories list

• caliptra-sw

  Public

  chipsalliance/caliptra-sw’s past year of commit activity
  Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

  Rust

  •

  Apache License 2.0

  •78•131•206•70•Updated Dec 18, 2025Dec 18, 2025

• Cores-VeeR-EL2

  Public
  VeeR EL2 Core

  fpgaprocessorriscv+ 11rtlrisc-vopen-source-hardwarefusesocverilatorriscv32western-digital+ 4

  SystemVerilog

  •

  Apache License 2.0

  •90•309•28•5•Updated Dec 18, 2025Dec 18, 2025

• verilator

  Public

  chipsalliance/verilator’s past year of commit activity
  Verilator open-source SystemVerilog simulator and lint system

  SystemVerilog

  •

  GNU Lesser General Public License v3.0

  •729•41•0•0•Updated Dec 18, 2025Dec 18, 2025

• t1

  Public
  Scala

  •

  Apache License 2.0

  •42•304•18•28•Updated Dec 18, 2025Dec 18, 2025

• chisel

  Public

  chipsalliance/chisel’s past year of commit activity
  Chisel: A Modern Hardware Design Language

  scalachip-generatorchisel+ 4rtlchisel3firrtlverilog

  Scala

  •

  Apache License 2.0

  •642•4.5k•348•143•Updated Dec 18, 2025Dec 18, 2025

• i3c-core

  Public

  chipsalliance/i3c-core’s past year of commit activity
  SystemVerilog

  •

  Apache License 2.0

  •16•38•14•7•Updated Dec 18, 2025Dec 18, 2025

• sv-tests-results

  Public

  chipsalliance/sv-tests-results’s past year of commit activity
  Output of the sv-tests runs.

  HTML

  •6•7•0•0•Updated Dec 18, 2025Dec 18, 2025

• caliptra-mcu-sw

  Public
  Caliptra MCU Software

  Rust

  •

  Apache License 2.0

  •33•21•86•14•Updated Dec 18, 2025Dec 18, 2025

• caliptra-ss

  Public

  chipsalliance/caliptra-ss’s past year of commit activity
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

  securityrotocp+ 3root-of-trustcaliptraopencomputeproject

  SystemVerilog

  •

  Apache License 2.0

  •31•34•74•8•Updated Dec 18, 2025Dec 18, 2025

• sv-tests

  Public

  chipsalliance/sv-tests’s past year of commit activity
  Test suite designed to check compliance with the SystemVerilog standard.

  rtlverilogsystemverilog+ 3hdlcompliance-testingsymbiflow

  SystemVerilog

  •

  ISC License

  •83•351•46•25•Updated Dec 17, 2025Dec 17, 2025

• caliptra-rtl

  Public
  HW Design Collateral for Caliptra RoT IP

  SystemVerilog

  •

  Apache License 2.0

  •70•123•96•20•Updated Dec 17, 2025Dec 17, 2025

• guineveer

  Public
  https://chipsalliance.github.io/guineveer/

  C

  •

  Apache License 2.0

  •2•3•0•0•Updated Dec 17, 2025Dec 17, 2025

• caliptra-dpe

  Public

  chipsalliance/caliptra-dpe’s past year of commit activity
  High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

  Rust

  •

  Apache License 2.0

  •28•20•23•9•Updated Dec 16, 2025Dec 16, 2025

• verible

  Public
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  productivityparserformatter+ 14analysisstyle-linterlinterlanguage-server-protocolsyntax-treelexeryacc+ 7

  C++

  •

  Other

  •263•1.7k•552•28•Updated Dec 12, 2025Dec 12, 2025

• adams-bridge

  Public
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)

  cryptographydigital-signaturelattice+ 2pqcml-dsa-87

  SystemVerilog

  •

  Apache License 2.0

  •8•41•17•1•Updated Dec 11, 2025Dec 11, 2025

• tac

  Public

  chipsalliance/tac’s past year of commit activity
  CHIPS Alliance Technical Advisory Council

  Apache License 2.0

  •26•7•17•3•Updated Dec 11, 2025Dec 11, 2025

• caliptra-web

  Public

  chipsalliance/caliptra-web’s past year of commit activity
  Astro

  •

  Apache License 2.0

  •5•0•0•0•Updated Dec 10, 2025Dec 10, 2025

• Caliptra

  Public
  Caliptra IP and firmware for integrated Root of Trust block

  Apache License 2.0

  •56•362•60•11•Updated Dec 9, 2025Dec 9, 2025

• chips-alliance-website

  Public

  chipsalliance/chips-alliance-website’s past year of commit activity
  SCSS

  •

  MIT License

  •7•4•8•8•Updated Dec 9, 2025Dec 9, 2025

• firrtl-spec

  Public
  The specification for the FIRRTL language

  TeX

  •30•62•25•17•Updated Dec 6, 2025Dec 6, 2025

• espresso

  Public
  C

  •18•41•7•0•Updated Dec 5, 2025Dec 5, 2025

• diplomacy

  Public

  chipsalliance/diplomacy’s past year of commit activity
  Scala

  •

  Apache License 2.0

  •16•22•9•1•Updated Dec 4, 2025Dec 4, 2025

• riscv-vector-tests

  Public
  Unit tests generator for RVV 1.0

  generatorspikeriscv+ 2testsuitervv

  Go

  •

  Apache License 2.0

  •32•98•11•1•Updated Nov 11, 2025Nov 11, 2025

• uvm-verilator

  Public

  chipsalliance/uvm-verilator’s past year of commit activity
  SystemVerilog

  •

  Apache License 2.0

  •23•110•1•0•Updated Nov 11, 2025Nov 11, 2025

• caliptra-ureg

  Public

  chipsalliance/caliptra-ureg’s past year of commit activity
  Rust

  •

  Apache License 2.0

  •6•7•0•1•Updated Nov 7, 2025Nov 7, 2025

• riscv-dv

  Public

  chipsalliance/riscv-dv’s past year of commit activity
  Random instruction generator for RISC-V processor verification

  Python

  •

  Apache License 2.0

  •366•1.2k•130•24•Updated Oct 1, 2025Oct 1, 2025

• chisel-template

  Public template

  chipsalliance/chisel-template’s past year of commit activity
  A template project for beginning new Chisel work

  Shell

  •

  The Unlicense

  •197•675•14•2•Updated Sep 22, 2025Sep 22, 2025

• verible-actions-common

  Public
  Apache License 2.0

  •8•2•0•0•Updated Sep 17, 2025Sep 17, 2025

• caliptra-infra

  Public

  chipsalliance/caliptra-infra’s past year of commit activity
  Various tools used for Caliptra's Continuous Integration flows

  Rust

  •

  Apache License 2.0

  •1•0•0•1•Updated Sep 16, 2025Sep 16, 2025

• .github

  Public
  Organization profile for CHIPS Alliance

  1•0•2•0•Updated Sep 16, 2025Sep 16, 2025