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    317 repositories

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •85•174•15•8•Updated Dec 16, 2025Dec 16, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •48•251•23•5•Updated Dec 16, 2025Dec 16, 2025

    • PeakRDL-rawheader

      Public
      Python
      •
      Apache License 2.0
      •2•0•1•1•Updated Dec 16, 2025Dec 16, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •20•89•2•3•Updated Dec 16, 2025Dec 16, 2025

    • artistic

      Public
      An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
      asicrenderinggdsii
      Python
      •
      Apache License 2.0
      •4•20•2•0•Updated Dec 16, 2025Dec 16, 2025

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •5•14•1•3•Updated Dec 15, 2025Dec 15, 2025

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •54•337•24•8•Updated Dec 15, 2025Dec 15, 2025

    • ace

      Public
      SystemVerilog
      •
      Other
      •6•20•0•1•Updated Dec 15, 2025Dec 15, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •91•115•23•6•Updated Dec 15, 2025Dec 15, 2025

    • magia-sdk

      Public
      C
      •6•4•0•1•Updated Dec 15, 2025Dec 15, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •31•57•15•9•Updated Dec 15, 2025Dec 15, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •36•127•1•12•Updated Dec 15, 2025Dec 15, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •186•686•33•11•Updated Dec 15, 2025Dec 15, 2025

    • pulp-nn-mixed

      Public
      C
      •9•12•1•0•Updated Dec 15, 2025Dec 15, 2025

    • llvm-project

      Public
      C++
      •15k•13•7•1•Updated Dec 14, 2025Dec 14, 2025

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •348•9•0•3•Updated Dec 14, 2025Dec 14, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •89•306•17•24•Updated Dec 12, 2025Dec 12, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •865•21•1•7•Updated Dec 12, 2025Dec 12, 2025

    • axi_riscv_atomics

      Public
      AXI Adapter(s) for RISC-V Atomic Operations
      SystemVerilog
      •
      Other
      •21•66•1•2•Updated Dec 12, 2025Dec 12, 2025

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •11•19•1•7•Updated Dec 12, 2025Dec 12, 2025

    • mempool

      Public
      A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •57•312•3•4•Updated Dec 12, 2025Dec 12, 2025

    • quadrilatero

      Public
      matrix-coprocessor for RISC-V
      C
      •
      Other
      •6•25•0•0•Updated Dec 12, 2025Dec 12, 2025

    • control-pulp

      Public
      C
      •
      Other
      •3•4•1•2•Updated Dec 12, 2025Dec 12, 2025

    • neureka

      Public
      2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
      SystemVerilog
      •
      Other
      •7•27•5•7•Updated Dec 11, 2025Dec 11, 2025

    • hwpe-ctrl

      Public
      IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •22•6•1•4•Updated Dec 11, 2025Dec 11, 2025

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •18•37•4•2•Updated Dec 11, 2025Dec 11, 2025

    • picobello

      Public
      whatever it means
      C
      •
      Other
      •8•13•7•1•Updated Dec 9, 2025Dec 9, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •330•1.4k•51•17•Updated Dec 9, 2025Dec 9, 2025

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •11•32•0•2•Updated Dec 8, 2025Dec 8, 2025

    • datamover

      Public
      SystemVerilog
      •
      Other
      •1•1•1•1•Updated Dec 8, 2025Dec 8, 2025