Random instruction generator for RISC-V processor verification

cocotb: Python-based chip (RTL) verification

System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers

Universal_Verification_Methodology ALU Example

Contains the code examples from The UVM Primer Book sorted by chapters.

uvm-1.2 library files from: http://www.accellera.org/images/downloads/standards/uvm/uvm-1.2.tar.gz

Design and UVM Verification of an ALU

A simple adder implementation and verification using UVM 1.2

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equ…

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.

This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based out-of-order core frontend and models memory scheduling polici…

Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay co…

RamulatorSharp is a fast and flexible memory subsystem simulator implemented in C# and it can easily run on Linux, OS X, and Windows. The simulator contains the implementation of the Low-Cost Inter…

Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA 2019 paper "CROW: A Low-Cost Substrate for Improving DRAM Pe…

This is a documentation for the final project of IEEE CUSB 23 Digital Electonics Workshop, the project was FPGA implemented

Implementation of a 5 stage MIPS pipelined processor in system verilog as described in Digital Design and Computer Architecture, 2nd Ed. by David Harris and Sarah Harris