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SMAesH Public
Forked from simple-crypto/SMAesHMasked Hardware AES with HPC
Verilog Other UpdatedApr 20, 2026 -
aaqdas.github.io Public
Academic Page (forked from academicpages/academicpages.github.io/)
JavaScript MIT License UpdatedApr 14, 2026 -
aes-128_pipelined_encryption Public
Forked from freecores/aes-128_pipelined_encryptionAES-128 Encryption
Verilog UpdatedApr 5, 2026 -
qemu Public
Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
C Other UpdatedFeb 20, 2026 -
riscinator Public
Forked from zyedidia/riscinatorA tiny 3-stage RISC-V core written in Chisel.
C MIT License UpdatedFeb 13, 2026 -
OCEAN Public
Forked from fam-emu/OCEANOCEAN – Open-source CXL Emulation at Hyperscale Architecture and Networking.
C UpdatedJan 8, 2026 -
The official repository for the gem5 computer-system architecture simulator.
C++ BSD 3-Clause "New" or "Revised" License UpdatedJan 4, 2026 -
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Trace-Driven-Cache-Simulator Public
Forked from Owen5u/Trace-Driven-Cache-SimulatorA simple trace driven cache simulator. Python version.
Python GNU General Public License v3.0 UpdatedJul 9, 2025 -
cvw Public
Forked from openhwgroup/cvwCORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
Verilog Other UpdatedJun 11, 2025 -
memory-latency Public
Forked from FedeParola/memory-latencyMemory latency test
C UpdatedApr 24, 2025 -
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Coyote Public
Forked from fpgasystems/CoyoteFramework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
SystemVerilog MIT License UpdatedJan 7, 2025 -
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doa_tuil Public
Direction of Arrival Implementation for TUIL Industrial Project
MATLAB UpdatedFeb 23, 2024 -
snntorch Public
Forked from jeshraghian/snntorchDeep and online learning with spiking neural networks in Python
Python MIT License UpdatedNov 27, 2023 -
vicuna Public
Forked from vproc/vicunaRISC-V Zve32x Vector Coprocessor
Assembly Other UpdatedSep 16, 2023 -
xor-memory-generator Public
XOR-Memory is a high-bandwidth memory. It can be used in Field Programmable Gate Arrays (FPGAs) to create a multi-ported memory using multiple banks of dual port memory (BRAMs).
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c-shenanigans Public
A repository holding various useful data structures and algorithms in C/C++
C++ MIT License UpdatedAug 14, 2023 -
ReadUART Public
Read An Flatten Image Array using UART and Echo The Results Back to MATLAB
MATLAB UpdatedAug 5, 2023 -
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wsi-scanner-segmentation Public
Whole Slide Image Segmentation
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bresenham-fpga Public
Verilog Implementation of Bresenham Circle Drawing Algorithm
Verilog MIT License UpdatedSep 23, 2022 -
riscv-scalar Public
Pipelined RV32I with Hazard Detection and Forwarding
Verilog MIT License UpdatedSep 23, 2022 -
wras Public
Water Reservoir Automation System - Digital Logic Design in Proteus
MIT License UpdatedSep 7, 2022 -
matlab-sheningans Public
The repository has many useful MATLAB functions and programs.
MATLAB MIT License UpdatedSep 7, 2022 -
FallDetection Public
Fall Detection is an Arduino based system that detects whether a person has fallen. It is helpful for older people who might fall and need immediate care and assistance.
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Analog-Clock Public
Analog Clock is x86 assembly based graphic program that generates an analog clock displaying current computer time
Assembly Apache License 2.0 UpdatedMar 29, 2022 -
Robotic-Arm Public
Robotic Arm is based on ATmega328P Microcontroller. The program is coded in Embedded C using Microchip Studio.
Makefile MIT License UpdatedMar 28, 2022
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