SVAUnit is a UVM-compliant verification framework designed to simplify the creation of stimuli and checkers for validating SystemVerilog Assertions (SVA).
This project is a revival and major refactor of the original open-source SVAUnit framework developed by AMIQ Consulting. Since January 2025, this version has been actively maintained, modernized, and extended with new features and a test-driven development focus.
- ✅ UVM-compliant structure for test environments
- ✅ Isolation of assertion behavior for unit-style testing
- ✅ Works with commercial simulators like Questa, VCS, and Xcelium
- ✅ Simplified test authoring for SVA-based verification
- ✅ Built-in stimulus and response API for assertion testing
Original blog series by AMIQ Consulting:
Coming Soon: Full documentation, example testbenches, and simulator setup instructions.
You can explore the codebase, examples, and test suites in the /src and /examples directories.
This framework is intended to be used within a UVM-compatible SystemVerilog simulation environment.
# Clone the repository
git clone https://github.com/your-handle/svaunit.gitMuneeb Ulla Shariff – Lead Contributor and Maintainer
📧 muneebullashariff@gmail.com
🌐 GitHub: muneebullashariff@gmail.com
Thanks to the original authors at AMIQ Consulting for open-sourcing the foundation of this work.
This project is a revival and major refactor of the original SVAUnit open-source framework.
Original foundation: [https://github.com/amiq-consulting/svaunit].
Refactored, extended, and actively maintained by Muneeb Ulla Shariff since 2025.
Copyright © 2025 Muneeb Ulla Shariff.
Distributed under the license present in the Repo. See the LICENSE file for full terms.